Datasheet

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed

while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation

of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

DESCRIPTION

X00 Sample inputs/toggle outputs (TOPSIP)

X01 Pseudo-random pattern generation/36-bit mode (PRPG)

X10 Parallel-signature analysis/36-bit mode (PSA)

011 Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)

111 Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)

While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,

the output-enable BSCs (bits 47–44 of the BSR) control the drive state (active or high impedance) of the selected

device output pins. These BCR instructions are valid only when both bytes of the device are operating in one

direction of data flow (that is, 1OEAB ≠ 1OEBA and 2OEAB ≠ 2OEBA) and in the same direction of data flow

(that is, 1OEAB = 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the

associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode

BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated

device I/O pins on each falling edge of TCK.