Datasheet

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A
SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
data register description
boundary-scan register
The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and
output data). The BSR is used to store test data that is to be applied externally to the device output pins, and/or
to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device
input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, BSCs 47–44 are reset to logic 1, ensuring that these cells, which control A-port and B-port
outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at high-impedance state).
Reset values of other BSCs should be considered indeterminate.
The BSR order of scan is from TDI through bits 47–0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
47 2OEAB 35 2A9-I/O 17 2B9-I/O
46 1OEAB 34 2A8-I/O 16 2B8-I/O
45 2OEBA 33 2A7-I/O 15 2B7-I/O
44 1OEBA 32 2A6-I/O 14 2B6-I/O
43 2CLKAB 31 2A5-I/O 13 2B5-I/O
42 1CLKAB 30 2A4-I/O 12 2B4-I/O
41 2CLKBA 29 2A3-I/O 11 2B3-I/O
40 1CLKBA 28 2A2-I/O 10 2B2-I/O
39 2LEAB 27 2A1-I/O 9 2B1-I/O
38 1LEAB 26 1A9-I/O 8 1B9-I/O
37 2LEBA 25 1A8-I/O 7 1B8-I/O
36 1LEBA 24 1A7-I/O 6 1B7-I/O
  23 1A6-I/O 5 1B6-I/O
  22 1A5-I/O 4 1B5-I/O
  21 1A4-I/O 3 1B4-I/O
  20 1A3-I/O 2 1B3-I/O
  19 1A2-I/O 1 1B2-I/O
  18 1A1-I/O 0 1B1-I/O