Datasheet

SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output terminals on each falling
edge of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the
inputs of the normal on-chip logic. Figures 5 and 6 show the 16-bit linear-feedback shift-register algorithms
through which the patterns are generated. An initial seed value should be scanned into the BSR before
performing this operation. A seed value of all zeroes does not produce additional patterns.
=
A8-I
B8-O
A7-I A6-I A5-I A4-I A3-I A2-I A1-I
B7-O B6-O B5-O B4-O B3-O B2-O B1-O
Figure 5. 16-Bit PRPG Configuration (OEAB = 1, OEBA = 1)
=
B8-I
A8-O
B7-I B6-I B5-I B4-I B3-I B2-I B1-I
A7-O A6-O A5-O A4-O A3-O A2-O A1-O
Figure 6. 16-Bit PRPG Configuration (OEAB = 0, OEBA = 0)