Datasheet

SN54ABT8652, SN74ABT8652

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed

while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation

of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

DESCRIPTION

X00 Sample inputs/toggle outputs (TOPSIP)

X01 Pseudo-random pattern generation/16-bit mode (PRPG)

X10 Parallel-signature analysis/16-bit mode (PSA)

011 Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)

111 Simultaneous PSA and binary count up/8-bit mode (PSA/COUNT)

In general, while the control input BSCs (bits 37–32) are not included in the sample, toggle, PSA, PRPG, or

COUNT algorithms, the output-enable BSCs (bits 37–36 of the BSR) do control the drive state (active or high

impedance) of the selected device output terminals. These BCR instructions are valid only when the device is

operating in one direction of data flow (that is, OEAB OEBA

). Otherwise, the bypass instruction is operated.

PSA input masking

Bits 10–3 of the BCR specify device input terminals to be masked from PSA operations. Bit 10 selects masking

for device input pin A8 during A-to-B data flow or for device input pin B8 during B-to-A data flow. Bit 3 selects

masking for device input terminals A1 or B1 during A-to-B or B-to-A data flow, respectively. Bits intermediate

to 10 and 3 mask corresponding device input terminals in order, from most significant to least significant, as

indicated in Table 3. When the mask bit that corresponds to a particular device input has a logic 1 value, the

device input pin is masked from any PSA operation, i.e., the state of the device input pin is ignored and has no

effect on the generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device

input is not masked from the PSA operation.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input terminals is captured in the shift-register elements of the selected

BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and

applied to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs

is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device

output terminals on each falling edge of TCK.