Datasheet

 

   

    

SCBS123F − AUGUST 1992 − REVISED APRIL 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the

shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the

shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same

time, an 8-bit pseudorandom pattern is generated in the shift-register elements of the selected output BSCs on

each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on

each falling edge of TCK. Figures 9 and 10 show the 8-bit linear-feedback shift-register algorithms through

which the signature and patterns are generated. An initial seed value should be scanned into the BSR before

performing this operation. A seed value of all zeroes does not produce additional patterns.

MASKX

A8-I

B8-O

A7-I A6-I A5-I A4-I A3-I A2-I A1-I

B7-O B6-O B5-O B4-O B3-O B2-O B1-O

Figure 9. 8-Bit PSA/PRPG Configuration (OEA = 0, OEB = 1)

MASKX

B8-I

A8-O

B7-I B6-I B5-I B4-I B3-I B2-I B1-I

A7-O A6-O A5-O A4-O A3-O A2-O A1-O

Figure 10. 8-Bit PSA/PRPG Configuration (OEA = 1, OEB = 0)