Datasheet

SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
parallel-signature analysis (PSA)
Data appearing at the selected device input pins is compressed into a 16-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow
latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow
latches of the selected output BSCs remains constant and is applied to the device outputs. Figures 6 and 7 show
the 16-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed
value should be scanned into the BSR before performing this operation.
=
=
MASKX
A8-I
B8-O
A7-I A6-I A5-I A4-I A3-I A2-I A1-I
B7-O B6-O B5-O B4-O B3-O B2-O B1-O
Figure 6. 16-Bit PSA Configuration (OEA = 0, OEB = 1)
=
=
MASKX
B8-I
A8-O
B7-I B6-I B5-I B4-I B3-I B2-I B1-I
A7-O A6-O A5-O A4-O A3-O A2-O A1-O
Figure 7. 16-Bit PSA Configuration (OEA = 1, OEB = 0)