Datasheet

SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT833 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT833 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT AND I/O
OEB OEA CLR
CLK
Ai
Σ OF H’s
Bi
Σ OF H’s
A B PARITY
ERR
FUNCTION
L
H
X
X
Odd
NA
NA
A
L
NA
A data to B bus and
L
H
X
X
Even
NA
NA
A
H
NA
generate parity
H
L
H
NA
Odd
B
NA
NA
H
B data to A bus and
H
L
H
NA
Even
B
NA
NA
L
check parity
X X L X X X X NA NA H Check error-flag register
H No X NC
§
H
H
LNo X
X
Z
Z
Z
H
Isolation
§
H
H
H Odd
X
Z
Z
Z
H
I
so
l
at
i
on
§
H Even L
L
L
X
X
Odd
NA
NA
A
H
NA
A data to B bus and
L
L
X
X
Even
NA
NA
A
L
NA
generate inverted parity
NA = not applicable, NC = no change, X = don’t care
Summation of high-level inputs includes PARITY along with Bi inputs.
Output states shown assume ERR
was previously high.
§
In this mode, ERR
(when clocked) shows inverted parity of the A bus.
logic symbol
ERR
CLR
OEA
OEB
CLR
11
CLK
13
CLK
1
2
A1
3
A2
4
A3
5
A4
10
PARITY
15
PARITY
B5
19
B6
18
B7
17
B8
16
8
OEA
1
OEB
14
6
A5
7
A6
8
A7
8
9
A8
B1
23
1
B2
22
B3
21
B4
20
ERR
Φ
A Bus B Bus
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.