Datasheet

SN74ABT18502
SCAN TEST DEVICE
WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS753 – FEBRUARY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
test architecture
Serial test information is conveyed by means of a four-wire test bus or TAP that conforms to IEEE Std
1149.1-1990. Test instructions, test data, and test control signals are all passed along this serial test bus. The
TAP controller monitors two signals from the test bus, namely TCK and TMS. The function of the TAP controller
is to extract the synchronization (TCK) and state control (TMS) signals from the test bus and generate the
appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP controller state
diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Std 1149.1-1990 four-wire test bus and boundary-scan
architecture and the relationship between the test bus, the TAP controller, and the test registers. As illustrated,
the device contains an 8-bit instruction register (IR) and four test data registers (DRs): an 84-bit boundary-scan
register (BSR), a 21-bit boundary-control register (BCR), a 1-bit bypass register, and a 32-bit device
identification register (IDR).
Test-Logic-Reset
Run-Test/Idle Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Update-DR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = LTMS = H
TMS = L
TMS = L
TMS = H
TMS = L
Exit2-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = LTMS = H
TMS = L
Exit2-IR
TMS = L
TMS = H TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = HTMS = H
TMS = H
TMS = L
Figure 1. TAP Controller State Diagram