Datasheet

SN74ABT18502
SCAN TEST DEVICE
WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS753 – FEBRUARY 2002
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
simultaneous PSA and COUNT (PSA/COUNT)
Data appearing at the selected device input pins is compressed into an 18-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 18-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. Figures 10 and 11 show the 18-bit linear-feedback shift-register algorithms through
which the signature is generated. An initial seed value should be scanned into the BSR prior to performing this
operation.
=
MASKX.X
1B8-O 1B7-O 1B6-O 1B5-O 1B4-O 1B3-O 1B2-O 1B1-O1B9-O
1A7-I 1A6-I 1A5-I 1A4-I 1A3-I 1A2-I 1A1-I1A8-I1A9-I
2A7-I 2A6-I 2A5-I 2A4-I 2A3-I 2A2-I 2A1-I2A8-I2A9-I
2B8-O 2B7-O 2B6-O 2B5-O 2B4-O 2B3-O 2B2-O 2B1-O2B9-O
=
MSB
LSB
Figure 10. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)