Datasheet

SN74ABT18502
SCAN TEST DEVICE
WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS753 – FEBRUARY 2002
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pseudorandom pattern generation (PRPG)
A pseudorandom pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 4 and 5 show the 36-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.
=
1B8-O 1B7-O 1B6-O 1B5-O 1B4-O 1B3-O 1B2-O 1B1-O1B9-O
1A7-I 1A6-I 1A5-I 1A4-I 1A3-I 1A2-I 1A1-I1A8-I1A9-I
2A7-I 2A6-I 2A5-I 2A4-I 2A3-I 2A2-I 2A1-I2A8-I2A9-I
2B8-O 2B7-O 2B6-O 2B5-O 2B4-O 2B3-O 2B2-O 2B1-O2B9-O
Figure 4. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)