Datasheet

SN74ABT18502

SCAN TEST DEVICE

WITH 18-BIT REGISTERED BUS TRANSCEIVER

SCBS753 – FEBRUARY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

BCR scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This

operation must be performed before a boundary-run test operation to specify which test operation is to be

executed.

BCR opcodes

The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 5. The selected test operation is performed

while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation

of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 5. BCR Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

DESCRIPTION

X00 Sample inputs/toggle outputs (TOPSIP)

X01 Pseudorandom pattern generation/36-bit mode (PRPG)

X10 Parallel signature analysis/36-bit mode (PSA)

011 Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)

111 Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)

In general, while the control-input BSCs (bits 83–72) are not included in the toggle, PSA, PRPG, or COUNT

algorithms, the output-enable BSCs (bits 83–80 of the BSR) control the drive state (active or high impedance)

of the selected device output pins. These BCR instructions are only valid when both bytes of the device are

operating in one direction of data flow (that is 1OEAB

≠ 1OEBA and 2OEAB ≠ 2OEBA) and in the same direction

of data flow (that is 1OEAB

= 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated.

PSA input masking

Bits 20–3 of the BCR are used to specify device input pins to be masked from PSA operations. Bit 20 selects

masking for device input pin 2A9 during A-to-B data flow or for device input pin 2B9 during B-to-A data flow.

Bit 3 selects masking for device input pins 1A1 or 1B1 during A-to-B or B-to-A data flow, respectively. Bits

intermediate to 20 and 3 mask corresponding device input pins in order from most significant to least significant,

as indicated in Table 2. When the mask bit that corresponds to a particular device input has a logic-1 value, the

device input pin is masked from any PSA operation, meaning that the state of the device input pin is ignored

and has no effect on the generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding

device input is not masked from the PSA operation.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs

on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied

to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs is

toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output

pins on each falling edge of TCK.