Datasheet

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t
c(n)
1/f0
0 V
0 V
Period Jitter
0 V Diff
Peak to Peak Jitter
1/f0
PRBS INPUT
OUTPUT
V
A
-V
B
or V
Y
-V
Z
V
A
-V
B
or V
Y
-V
Z
CLOCK
INPUT
IDEAL
OUTPUT
ACTUAL
OUTPUT
V
CC
V
CC
/2
t
jit(per)
= t
c(n)
-1/f0
t
jit(pp)
0 V
V
CC
V
CC
/2
0 V
V
A
-V
B
or V
Y
-V
Z
V
A
-V
B
or V
Y
-V
Z
(V
A
+ V
B
)/2
I
O
R
V
CM
V
O
V
ID
V
A
I
A
A
B
I
B
V
B
SN65MLVD201 , SN65MLVD203
SN65MLVD206 , SN65MLVD207
SLLS558C DECEMBER 2002 REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Maximum Steady State Output Voltage
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200Mbps 2
15
-1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
Figure 9. Receiver Voltage and Current Definitions
Copyright © 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207