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BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
DRIVER SWITCHING CHARACTERISTICS
SN65MLVD201 , SN65MLVD203
SN65MLVD206 , SN65MLVD207
SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
A
= 3.8 V, V
B
= 1.2 V, 0 32
Receiver or transceiver with driver
I
A
V
A
= 0 V or 2.4 V, V
B
= 1.2 V – 20 20 µ A
disabled input current
V
A
= – 1.4 V, V
B
= 1.2 V – 32 0
V
B
= 3.8 V, V
A
= 1.2 V 0 32
Receiver or transceiver with driver
I
B
V
B
= 0 V or 2.4 V, V
A
= 1.2 V – 20 20 µ A
disabled input current
V
B
= – 1.4 V, V
A
= 1.2 V – 32 0
Receiver or transceiver with driver
I
AB
disabled differential input current V
A
= V
B
, 1.4 ≤ V
A
≤ 3.8 V -4 4 µ A
(I
A
– I
B
)
V
A
= 3.8 V, V
B
= 1.2 V, 0 V ≤ V
CC
≤ 1.5 V 0 32
Receiver or transceiver power-off
I
A(OFF)
V
A
= 0 V or 2.4 V, V
B
= 1.2 V, 0 V ≤ V
CC
≤ 1.5 V – 20 20 µ A
input current
V
A
= – 1.4 V, V
B
= 1.2 V, 0 V ≤ V
CC
≤ 1.5 V – 32 0
V
B
= 3.8 V, V
A
= 1.2 V, 0 V ≤ V
CC
≤ 1.5 V 0 32
Receiver or transceiver power-off
I
B(OFF)
V
B
= 0 V or 2.4 V, V
A
= 1.2 V, 0 V ≤ V
CC
≤ 1.5 V – 20 20 µ A
input current
V
B
= – 1.4 V, V
A
= 1.2 V, 0 V ≤ V
CC
≤ 1.5 V – 32 0
Receiver input or transceiver
I
AB(OFF)
power-off differential input current V
A
= V
B
, 0 V ≤ V
CC
≤ 1.5 V, – 1.4 ≤ V
A
≤ 3.8 V – 4 4 µ A
(I
A
– I
B
)
Transceiver with driver disabled input
C
A
V
A
= 0.4 sin (30E6 π t) + 0.5V
(2)
, V
B
= 1.2 V 5 pF
capacitance
Transceiver with driver disabled input
C
B
V
B
= 0.4 sin (30E6 π t) + 0.5 V
(2)
, V
A
= 1.2 V 5 pF
capacitance
Transceiver with driver disabled
C
AB
V
AB
= 0.4 sin (30E6 π t)V
(2)
3 pF
differential input capacitance
Transceiver with driver disabled input
C
A/B
0.99 1.01
capacitance balance, (C
A
/C
B
)
(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 1 1.5 2.4 ns
t
PHL
Propagation delay time, high-to-low-level output 1 1.5 2.4 ns
t
r
Differential output signal rise time 1 1.6 ns
See Figure 5
t
f
Differential output signal fall time 1 1.6 ns
t
sk(p)
Pulse skew (|t
PHL
– t
PLH
|) 0 100 ps
t
sk(pp)
Part-to-part skew
(2)
1 ns
t
jit(per)
Period jitter, rms (1 standard deviation)
(3)
100 MHz clock input
(4)
2 3 ps
t
jit(pp)
Peak-to-peak jitter
(3) (5)
200 Mbps 2
15
– 1 PRBS input
(6)
30 130 ps
t
PHZ
Disable time, high-level-to-high-impedance output 7 ns
t
PLZ
Disable time, low-level-to-high-impedance output 7 ns
See Figure 6
t
PZH
Enable time, high-impedance-to-high-level output 7 ns
t
PZL
Enable time, high-impedance-to-low-level output 7 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(2) t
sk(pp)
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) t
r
= t
f
= 0.5 ns (10% to 90%), measured over 30 k samples.
(5) Peak-to-peak jitter includes jitter due to pulse skew (t
sk(p)
).
(6) t
r
= t
f
= 0.5 ns (10% to 90%), measured over 100 k samples.
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