Datasheet
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APPLICATION INFORMATION
Receiver Input Threshold (Failsafe)
-100
-50
0
50
100
150
200
Type 1
Transition Regions
Type 2
Low
High
Low
High
- Differential Input Voltage - mV
V
ID
SN65MLVD201 , SN65MLVD203
SN65MLVD206 , SN65MLVD207
SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and
have their differential input voltage thresholds near zero volts. Type 2 receivers have their differential input
voltage thresholds offset from zero volts to detect the absence of a voltage difference. The impact to receiver
output by the offset input can be seen in Table 3 and Figure 28 .
Table 3. Receiver Input Voltage Threshold Requirements
RECEIVER TYPE OUTPUT LOW OUTPUT HIGH
Type 1 – 2.4 V ≤ V
ID
≤ – 0.05 V 0.05 V ≤ V
ID
≤ 2.4 V
Type 2 – 2.4 V ≤ V
ID
≤ 0.05 V 0.15 V ≤ V
ID
≤ 2.4 V
Figure 28. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region
18 Submit Documentation Feedback Copyright © 2002 – 2007, Texas Instruments Incorporated
Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207