Datasheet

SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 3 5 6.7 ns
t
PHL
Propagation delay time, high-to-low-level output 3 4.6 6.7 ns
t
sk(p)
Pulse skew (|t
PHL
–- t
PLH
|)
C 5 pF See Figure 10
400 ps
t
sk(pp)
Part-to-part skew (see Note 9)
C
L
= 5 pF, See Figure 10
1.5 ns
t
r
Output signal rise time 0.8 1.4 2 ns
t
f
Output signal fall time 0.8 1.5 2 ns
t
PLH
Propagation delay time, low-to-high-level output 3.4 5.8 9 ns
t
PHL
Propagation delay time, high-to-low-level output 3.4 5.4 9 ns
t
sk(p)
Pulse skew (|t
PHL
–- t
PLH
|)
C 15 pF See Figure 10
400 ps
t
sk(pp)
Part-to-part skew (see Note 9)
C
L
= 15 pF, See Figure 10
2.5 ns
t
r
Output signal rise time 1 2 2.6 ns
t
f
Output signal fall time 1 1.4 2.6 ns
t
PHZ
Propagation delay time, high-level-to-high-impedance
output
4.5 6 15 ns
t
PLZ
Propagation delay time, low-level-to-high-impedance
output
See Figure 11
2 3.4 5 ns
t
PZH
Propagation delay time, high-impedance-to-high-level
output
See Figure 11
3.5 9.8 15 ns
t
PZL
Propagation delay time, high-impedance-to-low-level
output
4 8.7 15 ns
t
Period jitter, rms (1 standard deviation) 50-MHz clock input
Type 1 10
ps
t
jit(per)
Period
jitter
,
rms
(1
standard
deviation)
(see Notes 10 and 11)
50 MHz
clock
in ut
(see Figure 12)
Type 2 10
ps
t
Cycle to cycle jitter peak (see Notes 10 and 11)
50-MHz clock input
Type 1 93
ps
t
jit(cc)
Cycle-to-cycle jitter, peak (see Notes 10 and 11)
50 MHz
clock
in ut
(see Figure 12)
Type 2 86
ps
t
Peak to peak jitter (see Notes 10 12 and 13)
100 Mbps 2
15
–1 PRBS
Type 1 850
ps
t
jit(pp)
Peak-to-peak jitter, (see Notes 10, 12, and 13)
100
Mb s
2 1
PRBS
input (see Figure 12)
Type 2 790
ps
†
All typical values are at 25°C and with a 3.3-V supply voltage.
NOTES: 9. t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
10. Jitter parameters are based on design and characterization. Stimulus system jitter of 11 ps t
jit(per)
, 43 ps t
jit(cc)
, or 54 ps t
jit(pp)
have
been subtracted from the values.
11. Differential input voltage = 250 mV
p–p
(Type 1) or 500 mV
p–p
(Type 2), V
CM
= 1 V, t
r
= t
f
≤ 1 ns (20% to 80%), measured over 30k
samples.
12. Differential input voltage = 250 mV
p–p
(Type 1) or 500 mV
p–p
(Type 2), V
CM
= 1 V, t
r
= t
f
≤ 1 ns (20% to 80%), measured over 100k
samples.
13. Peak-to-peak jitter includes jitter due to pulse skew (t
sk(p)
).