Datasheet

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DRIVER SWITCHING CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
SN65MLVD200A , SN65MLVD202A
SN65MLVD204A , SN65MLVD205A
SLLS573 – DECEMBER 2003
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
pLH
Propagation delay time, low-to-high-level output 2 2.5 3.5 ns
t
pHL
Propagation delay time, high-to-low-level output 2 2.5 3.5 ns
t
r
Differential output signal rise time 2 2.6 3.2 ns
See Figure 5
t
f
Differential output signal fall time 2 2.6 3.2 ns
t
sk(p)
Pulse skew (|t
pHL
– t
pLH
|) 30 150 ps
t
sk(pp)
Part-to-part skew 0.9 ns
t
jit(per)
Period jitter, rms (1 standard deviation)
(2)
50 MHz clock input
(3)
2 3 ps
t
jit(pp)
Peak-to-peak jitter
(2) (4)
100 Mbps 2
15
-1 PRBS input
(5)
55 150 ps
t
PHZ
Disable time, high-level-to-high-impedance output 4 7 ns
t
PLZ
Disable time, low-level-to-high-impedance output 4 7 ns
See Figure 6
t
PZH
Enable time, high-impedance-to-high-level output 4 7 ns
t
PZL
Enable time, high-impedance-to-low-level output 4 7 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(3) t
r
= t
f
= 0.5 ns (10% to 90%), measured over 30 k samples.
(4) Peak-to-peak jitter includes jitter due to pulse skew (t
sk(p)
).
(5) t
r
= t
f
= 0.5 ns (10% to 90%), measured over 100 k samples.
over recommended operating conditions unless otherwise noted
TYP
(1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
(1)
t
PLH
Propagation delay time, low-to-high-level output 2 3.6 6 ns
t
PHL
Propagation delay time, high-to-low-level output 2 3.6 6 ns
t
r
Output signal rise time 1 2.3 ns
t
f
Output signal fall time C
L
= 15 pF, See Figure 10 1 2.3 ns
Type 1 100 300 ps
t
sk(p)
Pulse skew (|t
pHL
– t
pLH
|)
Type 2 300 500 ps
t
sk(pp)
Part-to-part skew
(2)
1 ns
t
jit(per)
Period jitter, rms (1 standard deviation)
(3)
50 MHz clock input
(4)
4 7 ps
Type 1 200 700 ps
t
jit(pp)
Peak-to-peak jitter
(3) (5)
100 Mbps 2
15
–1 PRBS input
(6)
Type 2 225 800 ps
t
PHZ
Disable time, high-level-to-high-impedance output 6 10 ns
t
PLZ
Disable time, low-level-to-high-impedance output 6 10 ns
See Figure 11
t
PZH
Enable time, high-impedance-to-high-level output 10 15 ns
t
PZL
Enable time, high-impedance-to-low-level output 10 15 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) V
ID
= 200 mV
pp
(LVD200A, 202A), V
ID
= 400 mV
pp
(LVD204A, 205A), V
cm
= 1 V, t
r
= t
f
= 0.5 ns (10% to 90%), measured over 30 k
samples.
(5) Peak-to-peak jitter includes jitter due to pulse skew (t
sk(p)
).
(6) V
ID
= 200 mV
pp
(LVD200A, 202A), V
ID
= 400 mV
pp
(LVD204A, 205A), V
cm
= 1 V, t
r
= t
f
= 0.5 ns (10% to 90%), measured over 100 k
samples.
6
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