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B
A
1.2V
Inputs
RE
C
15pF
L
V
O
R
499
L
W
V
TEST
t
PZL
t
PLZ
V
TEST
A
RE
V
O
V
TEST
A
RE
V
O
V
CC
0.8V
V
CC
0V
V +0.5V
OL
V
OL
V
CC
1.6V
0V
0V
V
CC
V
OH
V
OH
0V
t
PZH
t
PHZ
V
CC
2
V
CC
2
V
CC
2
V
CC
2
0.5V
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. R
L
is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T
C. C
L
is the instrumentation and fixture capacitance within 2 cm of the D.U.T. and ± 20%. The measurement is made on
test equipment with a –3dB bandwidth of at least 1GHz.
Figure 3. Receiver Enable/Disable Time Test Circuit and Waveforms
9
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