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Output
t
pLH
t
pHL
Input
0 V
0.9V
V
0 V
t
f
t
r
V
CC
V
CC
/2
0 V
SS
SS
0 V
0.1V
SS
SS
V
P(H)
V
P(L)
A
B
R1
24.9 Ω
t
pZH
t
pHZ
t
pZL
t
pLZ
V
CC
V
CC
/2
0 V
∼ 0.6 V
0.1 V
0 V
∼ -0.6 V
0 V
-0.1 V
EN
Output With
D at V
CC
Output
GND or V
CC
EN
Output With
D at GND
C1
1 pF
R2
24.9 Ω
C4
0.5 pF
C2
1 pF
D
C3
2.5 pF
Input
A
B
0 V or V
CC
1.62 kΩ, ±1%
V
A
or V
B
SN65MLVD128
SN65MLVD129
SLLS586 – MARCH 2004
PARAMETER MEASUREMENT INFORMATION (continued)
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. C1, C2, C3, and C4 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
Figure 7. Driver Maximum Steady State Output Voltage
7
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