Datasheet

www.ti.com
SWITCHING CHARACTERISTICS
SN65MLVD128
SN65MLVD129
SLLS586 – MARCH 2004
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output See Figure 5 1 3 ns
t
PHL
Propagation delay time, high-to-low-level output 1 3 ns
t
r
Differential output signal rise time 1 2 ns
t
f
Differential output signal fall time 1 2 ns
t
sk(p)
Pulse skew (|t
pHL
– t
pLH
|) 100 ps
t
sk(o)
Output skew 160 ps
t
sk(bb)
Bank-to-bank skew
(2)
100 ps
t
sk(pp)
Part-to-part skew
(3)
800 ps
t
jit(per)
Period jitter, rms (1 standard deviation)
(4)
100 MHz clock input, All channels enabled 1 3 ps
t
jit(c-c)
Cycle-to-cycle jitter
(4)
100 MHz clock input, All channels enabled 20 ps
200 Mbps 2
15
-1 PRBS input, All channels
t
jit(pp)
Peak-to-peak jitter
(4)
46 110 ps
enabled
t
PZH
Enable time, high-impedance-to-high-level output 7 ns
See Figure 6
t
PZL
Enable time, high-impedance-to-low-level output 7 ns
t
PHZ
Disable time, high-level-to-high-impedance output 7 ns
See Figure 6
t
PLZ
Disable time, low-level-to-high-impedance output 7 ns
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) t
sk(bb)
, which only applies to the SN65MLVD129, is the magnitude of the difference between the t
PLH
and t
PHL
of two outputs of any
bank.
(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Stimulus jitter has been subtracted from the numbers.
5
Submit Documentation Feedback