Datasheet

www.ti.com
APPLICATION INFORMATION
CLOCK DISTRIBUTION
Output duty cycle = 50.01%.
Vertical scale = 142 mV/div
Horizontal scale = 4 ns/div
SN65MLVD128 Output
Input Source: 61.44 MHz Clock With 50%
Duty Cycle, V
CC
= 3.3 V, R
L
= 50 , C
L
= 2.5 pF
Output Duty cycle = 49.97%.
Vertical scale = 142 mV/div
Horizontal scale = 11 ns/div
SN65MLVD128 Output
Input Source: 19.6608 MHz Clock With 50%
Duty Cycle, V
CC
= 3.3 V, R
L
= 50 , C
L
= 2.5 pF
DATA DISTRIBUTION
Vertical scale = 150 mV/div
Horizontal scale = 1.21 ns/div
SN65MLVD128 Output
Input Source: 250 Mbps, 2
15
-1 PRBS,
V
CC
= 3.3 V, R
L
= 50 , C
L
= 2.5 pF
SN65MLVD128
SN65MLVD129
SLLS586 – MARCH 2004
Figure 17. Figure 18.
Figure 19.
13
Submit Documentation Feedback