Datasheet

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A
B
0 V or V
CC
1.62 kΩ , ±1%
V
A
or V
B
t
c(n)
1/f0
0 V
0 V
Period Jitter
0 V
Peak to Peak Jitter
1/f0
PRBS INPUT
OUTPUT
V
A
-V
B
V
A
-V
B
CLOCK
INPUT
IDEAL
OUTPUT
ACTUAL
OUTPUT
V
CC
V
CC
/2
t
jit(per)
= t
c(n)
-1/f0
t
jit(pp)
0 V
V
CC
V
CC
/2
0 V
V
A
-V
B
V
A
-V
B
Cycle to Cycle Jitter
0 V
V
A
- V
B
OUTPUT
t
c(n)
t
c(n+1)
t
jit(cc)
= | t
c(n)
- t
c(n+1)
|
(V
A
+ V
B
)/2
I
O
R
V
CM
V
O
V
ID
V
A
I
A
A
B
I
B
V
B
SN65MLVD080
SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Maximum Steady State Output Voltage
A. All input pulses are supplied by an Agilent 8304A Stimulus System with plug-in TBD.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ± 1% duty cycle clock input.
D. Peak-to-peak jitter and deterministic jitter are measured using a 200 Mbps 2
15
–1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
Figure 9. Receiver Voltage and Current Definitions
9
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