Datasheet

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f  45% 
1
2  t
transition
(1)
SN65MLVD080
SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
APPLICATION INFORMATION (continued)
t
sk(o)Source
= 2.0 ns – Output skew of data processing unit; any skew between data bits, or clock and data bits
t
sk(p-p)DRVR
= 0.6 ns – Driver part-to-part skew of the SN65MLVD082
t
sk(flight)BP
= 0.4 ns – Skew of propagation delay on the backplane between data and clock
t
sk(p-p)RCVR
= 1.0 ns – Receiver part-to-part skew of the SN65MLVD082
The 238-MHz maximum operating speed calculated above was determined based on data and clock skews only.
Another important consideration when calculating the maximum operating speed is output transition time.
Transition-time-limited operating speed can be calculated from the following formula:
Using the typical transition time of the SN65MLVD082 of 1.4 ns, a transition-time-limited operating frequency of
170 MHz can be supported.
In addition to the high operating frequencies of SSSC that can be ensured, the SN65MLVD082 presents other
benefits as other M-LVDS bus transceivers can provide:
• Robust system operation due to common mode noise cancellation using a low voltage differential receiver
• Low EMI radiation noise due to differential signaling improves signal integrity through the backplane
• A singly terminated transmission line is easy to design and implement
• Low power consumption in both active and idle modes minimizes thermal concerns on each module
In dense backplane design, these benefits are important for improving the performance of the whole system.
A similar result can be achieved with the SN65MLVD080.
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