Datasheet

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APPLICATION INFORMATION
Source Synchronous System Clock (SSSC)
Modules 1
Data Width1 15
Modules N
Data Width1 15
Main System Clock
Timing
Process
Unit
MLVD206
1Tx 1Rx
MLVD206
1Tx 1Rx
MLVD206
1Tx 1Rx
MLVD080/082 (x2)
8Tx 8Rx
tsk(flight)BP
tsk(o)Source
tsk(p-p)RCVR
tsk(p-p)DRVR
Data Process Unit
ASIC/FPGA
uController
Subsystem
Clock
Timing
Process
Unit
Data Process Unit
ASIC/FPGA
uController
Centralized - Synchronous Main System Clock M - LVDS Differential Bus
80~100 Ω R
T
Subsystem
Clock
MLVD080/082 (x2)
8Tx 8Rx
80~100 Ω R
T
80~100 Ω R
T
Source - Synchronous Subsystem Clock M - LVDS Differential Bus
M- LVDS Backplane
80~100 Ω R
T
80~100 Ω R
T
Number of Modules
Data/Control M - LVDS Differential Bus #1 ~ #15
80~100 Ω R
T
SN65MLVD080
SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
There are two approaches to transmit data in a synchronous system: centralized synchronous system clock
(CSSC) and source synchronous system clock (SSSC). CSSC systems synchronize data transmission between
different modules using a clock signal from a centralized source. The key requirement for a CSSC system is for
data transmission and reception to complete during a single clock cycle. The maximum operating frequency is
the inverse of the shortest clock cycle for which valid data transmission and reception can be ensured. SSSC
systems achieve higher operating frequencies by sending clock and data signals together to eliminate the flight
time on the transmission media, backplane, or cables. In SSSC systems, the maximum operating frequency is
limited by the cumulated skews that can exist between clock and data. The absolute flight time of data on the
backplane does not provide a limitation on the operating frequency as it does with CSSC.
The SN65MLVD082 can be designed for interfacing the data and clock to support source synchronous system
clock (SSSC) operation. It is specified for transmitting data up to 250 Mbps and clock frequencies up to 125
MHz. The figure below shows an example of a SSSC architecture supported by M-LVDS transceivers. The
SN65MLVD206, a single channel transceiver, transmits the main system clock between modules. A retiming unit
is then applied to the main system clock to generate a local clock for subsystem synchronization processing.
System operating data (or control) and subsystem clock signals are generated from the data processing unit,
such as a microprocessor, FPGA, or ASIC, on module 1, and sent to slave modules through the SN65MLVD082.
Such design configurations are common while transmitting parallel control data over the backplane with a higher
SSSC subsystem clock frequency. The subsystem clock frequency is aligned with the operating frequencies of
the data processing unit to synchronize data transmission between different units.
Figure 37. Using Differential M-LVDS to Perform Source Synchronous System Clock Distribution
The maximum SSSC frequencies in a transparent mode can be calculated with the following equation:
f
max(clk)
< 1/[ t
sk(o)Source
+ t
sk(p-p)DRVR
+ t
sk(flight)BP
+ t
sk(p-p)RCVR
Setup time and hold time on the receiver side are decided by the data processing unit, FPGA, or ASIC in this
example. By considering data passes through the transceiver only, the general calculation result is 238 MHz
when using the following data:
21
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