Datasheet

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t
c(n)
1/f0
Period Jitter
Peak to Peak Jitter
1/f0
PRBS INPUT
OUTPUT
CLOCK INPUT
IDEAL
OUTPUT
ACTUAL
OUTPUT
t
jit(per)
= t
c(n)
-1/f0
t
jit(pp)
V
A
-V
B
INPUTS
V
A
- V
B
V
CM
0.2 V (’080) 1 V
0.4 V (’082)
V
OH
V
CC
/2
V
OL
V
OH
V
OL
V
CC
/2
V
OH
V
OL
V
CC
/2
V
A
V
B
Cycle to Cycle Jitter
V
OH
V
CC
/2
V
OL
OUTPUT
t
c(n)
t
c(n+1)
t
jit(cc)
= | t
c(n)
- t
c(n+1)
|
SN65MLVD080
SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
A. All input pulses are supplied by an Agilent 8304A Stimulus System with plug-in TBD.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ± 1% duty cycle clock input.
D. Peak-to-peak jitter and deterministic jitter are measured using a 200 Mbps 2
15
–1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
Table 3. Terminal Functions
PIN
TYPE DESCRIPTION
NAME NO.
1D–8D 58, 57, 52, 51, 46, 45, 40, 39 Input Data inputs for drivers
1R–8R 59, 56, 53, 50, 47, 44, 41, 38 Output Data output for receivers
1A–8A 6, 8, 12, 14, 18, 20, 24, 26 Bus I/O M-LVDS bus noninverting input/output
1B–8B 7, 9, 13, 15, 19, 21, 25, 27 Bus I/O M-LVDS bus inverting input/output
10, 16, 22, 28, 36, 37, 43, 49, 55, 62, 63,
GND Power Circuit ground
64
V
CC
5, 11, 17, 23, 34, 35, 42, 48, 54, 60, 61 Power Supply voltage
RE 33 Input Receiver enable, active low, enables all receivers
1DE–8DE 1, 2, 3, 4, 29, 30, 31, 32 Input Driver enable, active high, individual enables
12
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