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1.2 V
1.0 V
t
pLH
0.2 V
-0.2 V
V
A
V
B
V
ID
90%
V
OH
V
OL
t
pHL
10%
t
f
t
r
V
O
V
CC
/2
V
O
V
ID
V
B
V
A
C
L
0 V
15 pF
SN65MLVD080
SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
Table 1. Type-1 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL RESULTING COMMON-
APPLIED VOLTAGES
RECEIVER
INPUT VOLTAGE MODE INPUT VOLTAGE
OUTPUT
(1)
V
IA
V
IB
V
ID
V
IC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.400 3.350 0.050 3.375 H
3.350 3.400 –0.050 3.375 L
–1.350 –1.400 0.050 –1.375 H
–1.400 –1.350 –0.050 –1.375 L
(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)
Table 2. Type-2 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL RESULTING COMMON-
APPLIED VOLTAGES
RECEIVER
INPUT VOLTAGE MODE INPUT VOLTAGE
OUTPUT
(1)
V
IA
V
IB
V
ID
V
IC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.400 3.250 0.150 3.325 H
3.400 3.350 0.050 3.375 L
–1.250 –1.400 0.150 –1.325 H
–1.350 –1.400 0.050 –1.375 L
(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%. C
L
is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture
capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 10. Receiver Timing Test Circuit and Waveforms
10
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