Datasheet

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DEVICE ELECTRICAL CHARACTERISTICS
SN65MLVD047
SLLS606A MARCH 2004 REVISED JULY 2005
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN
(1)
TYP
(2)
MAX UNIT
LVTTL (EN, EN, 1A:4A)
|I
IH
| High-level input current V
IH
= 2 V or V
CC
0 10 µ A
|I
IL
| Low-level input current V
IL
= GND or 0.8 V 0 10 µ A
C
i
Input capacitance V
I
= 0.4 sin(30E6 π t) + 0.5 V
(3)
5 pF
M-LVDS (1Y/1Z:4Y/4Z)
|V
YZ
| Differential output voltage magnitude 480 650 mV
See Figure 2
Change in differential output voltage magnitude
|V
YZ
| –50 50 mV
between logic states
V
OS(SS)
Steady-state common-mode output voltage 0.8 1.2 V
Change in steady-state common-mode output
V
OS(SS)
See Figure 3 –50 50 mV
voltage between logic states
V
OS(PP)
Peak-to-peak common-mode output voltage 150 mV
Maximum steady-state open-circuit output volt-
V
Y(OC)
0 2.4 V
age
See Figure 7
Maximum steady-state open-circuit output volt-
V
Z(OC)
0 2.4 V
age
V
P(H)
Voltage overshoot, low-to-high level output 1.2 V
SS
V
See Figure 5
V
P(L)
Voltage overshoot, high-to-low level output –0.2 V
SS
V
Differential short-circuit output current magni-
|I
OS
| See Figure 4 24 mA
tude
–1.4 V (V
Y
or V
Z
) 3.8 V,
I
OZ
High-impedance state output current –15 10 µ A
Other output = 1.2 V
–1.4 V (V
Y
or V
Z
) 3.8 V,
I
O(OFF)
Power-off output current –10 10 µ A
Other output = 1.2 V, V
CC
= 0 V
V
Y
or V
Z
= 0.4 sin(30E6 π t) + 0.5 V,
(3)
C
Y
or C
Z
Output capacitance 3 pF
Other input at 1.2 V, driver disabled
V
YZ
= 0.4 sin(30E6 π t) V,
(3)
C
YZ
Differential output capacitance 2.5 pF
Driver disabled
C
Y/Z
Output capacitance balance, (C
Y
/C
Z
) 0.99 1.01
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25 ° C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)
4