Datasheet
SN65MLVD047A
SLLS736A − JULY 2006 − REVISED MAY 2008
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER PACKAGE MARKING PACKAGE/CARRIER
SN65MLVD047AD MLVD047A 16-Pin SOIC/Tube
SM65MLVD047ADR MLVD047A 16-Pin SOIC/Tape and Reel
SN65MLVD047APW BUL 16-Pin TSSOP/Tube
SM65MLVD047APWR BUL 16-Pin TSSOP/Tape and Reel
NOTE
:
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
PACKAGE DISSIPATION RATINGS
PACKAGE
PCB JEDEC
STANDARD
T
A
≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE T
A
= 25°C
(1)
T
A
= 85°C
POWER RATING
D(16) Low-K
(2)
898 mW 7.81 mW/_C 429 mW
PW(16)
Low-K
(2)
592 mW 5.15 mW/_C 283 mw
PW(16)
High-K
(3)
945 mW 8.22 mW/_C 452 mw
(1)
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
(2)
In accordance with the Low-K thermal metric difinitions of EIA/JESD51−3.
(3)
In accordance with the High-K thermal metric difinitions of EIA/JESD51−7.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNITS
Supply voltage range
(2)
, V
CC
−0.5 V to 4 V
Input voltage range, V
I
A, EN, EN −0.5 V to 4 V
Output voltage range, V
O
Y, Z −1.8 V to 4 V
Human Body Model
(3)
Y and Z ±9 kV
Electrostatic discharge
Human Body Model
(3)
All pins ±4 kV
Electrostatic discharge
Charged-Device Model
(4)
All pins ±1500 V
Machine Model
(5)
All pins 200 V
Junction temperature, T
J
140°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values, except differential I/O bus voltages, are with respect to the circuit ground terminal.
(3)
Tested in accordance with JEDEC Standard 22, Test Method A114−B.
(4)
Tested in accordance with JEDEC Standard 22, Test Method C101−A.
(5)
Tested in accordance with JEDEC Standard 22, Test Method A115−A.