Datasheet
SN65MLVD047A
SLLS736 − JULY 2006
www.ti.com
12
APPLICATION INFORMATION
SYNCHRONIZATION CLOCK IN ADVANCEDTCA
Advanced Telecommunications Computing Architecture, also known as AdvancedTCA, is an open architecture to meet
the needs of the rapidly changing communications network infrastructure. M−LVDS bused clocking is recommended by
the ATCA.
The ATCA specification includes requirements for three redundant clock signals. An 8-KHz and a 19.44-MHz clock signal,
as well as an user-defined clock signal are included in the specification. The SN65MLVD047A quad driver supports
distribution of these three ATCA clock signals, supporting operation beyond 100 MHz, which is the highest clock frequency
included in the ATCA specification. A pair of SN65MLVD047A devices can be used to support the ATCA redundancy
requirements.
MULTIPOINT CONFIGURATION
The SN65MLVD047A is designed to meet or exceed the requirement of the TIA/EIA−899 (M−LVDS) standard, which allows
multipoint communication on a shared bus.
Multipoint is a bus configuration with multiple drivers and receivers present. An example is shown in Figure 17. The figure
shows transceivers interfacing to the bus, but a combination of drivers, receivers, and transceivers is also possible.
Termination resistors need to be placed on each end of the bus, with the termination resistor value matched to the loaded
bus impedance.
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Figure 17. Multipoint Architecture
MULTIDROP CONFIGURATION
Multidrop configuration is similar to multipoint configuration, but only one driver is present on the bus. A multidrop system
can be configured with the driver at one end of the bus, or in the middle of the bus. When a driver is located at one end,
a single termination resistor is located at the far end, close to the last receiver on the bus. Alternatively, the driver can be
located in the middle of the bus, to reduce the maximum flight time. With a centrally located driver, termination resistors
are located at each end of the bus. In both cases the termination resistor value should be matched to the loaded bus
impedance. Figure 18 shows examples of both cases.