Datasheet
SN65LVPE504
SLLSE46 –SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
under recommended operating conditions
PARAMETER CONDITIONS MIN TYP MAX UNITS
TRANSMITTER AC/DC
RL = 100Ω ±1%, OS = NC, transition Bit 866 929 1031
RL = 100Ω ±1%, OS = GND transition Bit 800
RL = 100Ω ±1% OS = VCC transition Bit 1047
Differential peak-to-peak
V
TXDIFF_P-P
mV
RL = 100Ω ±1%, DE=NC, OS = 0,1,NC
output voltage
620
on-transition bit
RL = 100Ω ±1%, DE=OS = 0,1,NC on-transition bit 456
RL = 100Ω ±1%, DE=OS = 0,1,NC on-transition bit 288
–3.0 –3.4 –4.0
OS = NC (Figure 9) for OS = 1 and NC see
De-emphasis level –5.5 –6.2 –6.5 dB
Table 1)
–9.0 –10.3 –10.6
T
DE
De-emphasis width At 5 Gbps 0.9 UI
Z
TX_diff
DC Differential impedance Defined during signaling 80 100 120 Ω
f = 50 MHz – 1.25 GHz 10 20
RL
diff_TX
Differential return loss dB
f = 1.25 GHz – 2.5 GHz 8 13
RL
CM_TX
Common mode return loss f = 50 MHz – 2.5 GHz 6 12 dB
I
TX_SC
TX short circuit current TX± shorted to GND 44 90 mA
Transmitter DC common-mode Allowed DC CM voltage at TX pins
V
TX_CM_DC
1.8 2.2 V
voltage
TX AC common mode voltage Max(V
d+
+ V
d–
) /2 – Min(V
d+
+ V
d–
)/2
V
TX_CM_AC2
30 100 mVpp
at Gen II speed
TX AC common mode voltage RMS(V
d+
+ V
d–
)/2 – DC
AVG
(V
d+
+ V
d–
)/2
V
TX_CM_AC1
3 20 mV
at Gen I speed
V
TX_CM_DeltaL0-
Absolute Delta DC CM voltage |V
TX_CM_DC [L0]
– VTX_CM_DC [L0
s
] |
0 100 mV
L0s
during active and idle states
V
TX_CM-DC-Line-
Absolute delta of DC CM |V
TX_CM_DC–D+ [L0]
– V
TX_CM_DC–D– [L0]
|
0 25 mV
Delta
voltage between D+ and D–
Electrical idle differential peak |V
TX-Idle-D+
– V
TX-Idle-D–
|, LP filtered to remove any
V
TX_idle_diff-AC-p
0 1 20 mVpp
output voltage DC component
DC electrical idle differential |V
TX_idle-D+
– V
TX_idle-D–
|, LP filtered to remove any
V
TX_idle_diff-DC
1.9 mV
output voltage AC component
Voltage change to allow Positive voltage to sense receiver
V
detect
600 mV
receiver detect
De-Emphasis = 0 dB,
t
R
,t
F
Output rise/fall time OS = NC (CH 0 and CH 1) 30 55 70 ps
20%-80% of differential voltage at the output
De-Emphasis = 0dB,
t
RF_MM
Output rise/fall time mismatch OS = NC (CH 0 and CH 1) 20 ps
20%-80% of differential voltage at the output
De-Emphasis = 0dB (CH 0 and CH 1). Propagation
T
diff_LH
, T
diff_HL
Differential propagation delay 280 350 ps
delay between 50% level at input and output
T
INTRA_SKEW
Output skew (same lane) 5 Gbps 15 ps
T
INTER_SKEW
Lane to lane skew 5 Gbps –25 25 ps
t
idleEntry
, t
idleExit
Idle entry and exit times See Figure 5 8 ns
T
tx_EID_min
Minimum time in EID 20 ns
Tx EQUALIZATION AT GEN II SPEED
TX
DJ
(1)
At point A1 in Figure 8, EQ/DE=NC, OS=HIGH 25 60
Residual deterministic jitter At point A2 in Figure 8, EQ/DE=NC, OS=LOW 26 60 ps p-p
At point B in Figure 8, EQ/DE=NC, OS=HIGH 27 60
TX
RJ
Residual random jitter D24.3 pattern at point A1/A2/B in Figure 8 0.1 psrms
(1) Refer to Figure 8 with ±K28.5 pattern, –3.5dB DE from source AWG
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