Datasheet

VCC
PS2 OS EN_RXD RST
VCC
VCC
EQ
SQ_TH
DE
PS1
NC NC
NCNC
GND GND
GND
GND
GND
GND
GND
GND
RX1+ TX1+
TX2+
TX3+
TX4+
RX2+
RX3+
RX4+
RX1– TX1–
TX2–
TX3–
TX4–
RX2–
RX3–
RX4–
VCC
VCC
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
RUA Package
(TopView)
SN65LVPE504
SN65LVPE504
SLLSE46 –SEPTEMBER 2010 www.ti.com
DEVICE INFORMATION
Figure 3. Flow-Through Pin-Out
PIN FUNCTIONS
PIN
I/O TYPE DESCRIPTION
NO. NAME
HIGH SPEED DIFFERENTIAL I/O PINS
3 RX1+
4 RX1–
6 RX2+
7 RX2–
Non-inverting and inverting CML differential input for CH 1 and CH 4. These pins are tied to an internal voltage
I, CML
bias by dual termination resistor circuit
11 RX3+
12 RX3–
14 RX4+
15 RX4–
36 TX1+
35 TX1–
Non-inverting and inverting CML differential output for CH 1 and CH 4. These pins are internally tied to voltage
O, CML
bias by termination resistors
33 TX2+
32 TX2–
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