Datasheet

SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
(1)
PART NUMBER OF TERMINATION SYMBOLIZATION
NUMBER
(2)
RECEIVERS RESISTOR
SN65LVDS33D 4 No LVDS33
SN65LVDS33PW 4 No LVDS33
SN65LVDTS33D 4 Yes LVDT33
SN65LVDT33PW 4 Yes LVDT33
SN65LVDS34D 2 No LVDS34
SN65LVDT34D 2 Yes LVDT34
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Add the suffix R for taped and reeled carrier.
DESCRIPTION (CONTINUED)
The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or
powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of
the SN65LVDS32B application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from –40°C
to 85°C.
Table 1. Function Tables
(1)
SN65LVDS33 and SN65LVDT33 SN65LVDS34 and SN65LVDT34
DIFFERENTIAL INPUT ENABLES OUTPUT DIFFERENTIAL INPUT OUTPUT
V
ID
= V
A
- V
B
G G Y V
ID
= V
A
– V
B
Y
H X H V
ID
≥ –32 mV H
V
ID
≥ –32 mV
X L H –100 mV < V
ID
≤ –32 mV ?
H X ? V
ID
≤ –100 mV L
–100 mV < V
ID
≤ –32 mV
X L ? Open H
H X L
V
ID
≤ –100 mV
X L L
X L H Z
H X H
Open
X L H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
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Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34