Datasheet

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OUTPUT ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN65LVDS250
SN65LVDT250
SLLS594B – MARCH 2004 – REVISED OCTOBER 2004
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
OD
| Differential output voltage magnitude 247 350 454 mV
See Figure 2
V
ID
= ± 100 mV
∆ |V
OD
| Change in differential output voltage magnitude between logic states -50 50 mV
V
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output voltage between logic
∆ V
OC(SS)
See Figure 3 -50 50 mV
states
V
OC(PP)
Peak-to-peak common-mode output voltage 50 150 mV
I
CC
Supply current R
L
=100 Ω 110 145 mA
I
OS
Short-circuit output current V
OY
or V
OZ
= 0 V -27 27 mA
I
OSD
Differential short circuit output current V
OD
= 0 V -12 12 mA
I
OZ
High-impedance output current V
O
= 0 V or V
CC
± 1 µA
C
O
Differential output capacitance 2 pF
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 700 800 1200
t
PHL
Propagation delay time, high-to-low-level output 700 800 1200
See Figure 4 ps
t
r
Differential output signal rise time (20%-80%) 200 245
t
f
Differential output signal fall time (20%-80%) 200 245
t
sk(p)
Pulse skew (|t
PHL
- t
PLH
|)
(1)
0 50 ps
t
sk(o)
Channel-to-channel output skew
(2)
175 ps
t
sk(pp)
Part-to-part skew
(3)
300 ps
t
jit(per)
Period jitter, rms (1 standard deviation)
(4)
See Figure 6 1 3 ps
t
jit(cc)
Cycle-to-cycle jitter (peak)
(5)
See Figure 6 8 17 ps
t
jit(pp)
Peak-to-peak jitteR
(6)
See Figure 6 60 110 ps
t
jit(det)
Deterministic jitter, peak-to-peak
(7)
See Figure 6 48 65 ps
t
PHZ
Propagation delay, high-level-to-high-impedance output 6
t
PLZ
Propagation delay, low-level-to-high-impedance output 6
See Figure 5 ns
t
PZH
Propagation delay, high-impedance -to-high-level output 300
t
PZL
Propagation delay, high-impedance-to-low-level output 300
(1) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any output of a single device.
(2) t
sk(o)
is the maximum delay time difference between drivers over temperature, V
CC
, and process.
(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Input voltage = V
ID
= 200 mV, 50% duty cycle at 1.0 GHz, t
r
= t
f
= 50 ps (20% to 80%), measured over 1000 samples.
(5) Input voltage = V
ID
= 200 mV, 50% duty cycle at 1.0 GHz, t
r
= t
f
= 50 ps (20% to 80%).
(6) Input voltage = V
ID
= 200 mV, 2
23
-1 PRBS pattern at 2.0 Gbps, t
r
= t
f
= 50 ps (20% to 80%), measured over 200k samples.
(7) Input voltage = V
ID
= 200 mV, 2
7
-1 PRBS pattern at 2.0 Gbps, t
r
= t
f
= 50 ps (20% to 80%).
6