Datasheet

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1A
1B
5Y
5Z
1R
5D
2A
2B
2R
3A
3B
3R
4A
4B
4R
1Y
1Z
1D
2Y
2Z
2D
3Y
3Z
3D
4Y
4Z
4D
5A
5B
5R
1Y
1Z
1D
1A
1B
5Y
5Z
1R
5D
2Y
2Z
2D
2A
2B
2R
3Y
3Z
3D
3A
3B
3R
4Y
4Z
4D
4A
4B
4R
5A
5B
5R
SCLK
BS
DIR
SD1
SD2
CBT
SCLK
BS
SDIO
Memory
Stick
CBT
SCLK
BS
SDIO
DIR
Memory
Stick
Host
Controller
SN65LVDT41 SN65LVDT14
Absolute Maximum Ratings
(1)
SN65LVDT14-EP, SN65LVDT41-EP
SCES633 – JUNE 2005
SN65LVDT41 LOGIC DIAGRAM SN65LVDT14 LOGIC DIAGRAM
(POSITIVE LOGIC) (POSITIVE LOGIC)
TYPICAL MEMORY STICK INTERFACE EXTENSION
over operating free-air temperature range (unless otherwise noted)
SN65LVDT14,
SN65LVDT41
UNIT
MIN MAX
V
CC
Supply voltage range
(2)
–0.5 4 V
D or R –0.5 6
Input voltage range V
A, B, Y, or Z –0.5 4
A, B, Y, Z, and GND ± 12
Human-Body Model
(3)
KV
Electrostatic discharge All pins ± 8
Charged-Device Model
(4)
All pins ± 500 V
Continuous total power dissipation See Dissipation Rating Table
Storage temperature range –65 150 ° C
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260 ° C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A
(4) Tested in accordance with JEDEC Standard 22, Test Method C101
2