Datasheet

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at clock periods other than 15.38 ns can be calculated from
tc
14
–600 ps.
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN65LVDS96
SLLS296H – MAY 1998 – REVISED JULY 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential Input voltage threshold 100 mV
V
IT-
Negative-going differential Input voltage threshold
(2)
–100 mV
V
OH
High-level output voltage I
OH
= –4 mA 2.4 V
V
OL
Low-level output voltage I
OH
= 4 mA 0.4 V
Disabled, all inputs open 280 µ A
Enabled, AnP at 1 V and AnM at 1.4 V,
60 82
I
CC
Quiescent current (average) t
c
= 15.38 ns
mA
Enabled, C
L
= 8 pF, Worst-case pattern
94
(see Figure 4 ), t
c
= 15.38 ns
I
IH
High-level input current ( SHTDN) V
IH
= V
CC
± 20 µ A
I
IL
Low-level input current ( SHTDN) V
IL
= 0 V ± 20 µ A
I
IN
Input current (A inputs) 0 V ≤ V
I
≤ 2.4 V ± 20 µ A
I
OZ
High-impedance output current V
O
= 0 V to V
CC
± 10 µ A
(1) All typical values are V
CC
= 3.3 V, T
A
= 25 ° C.
(2) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going input voltage threshold only.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
su
Data setup time, D0 through D20 to CLKOUT ↑ 3.4 6
C
L
= 8 pF, See Figure 5 ns
t
h
Data hold time, CLKOUT ↑ to D0 through D20 4 6
T
A
= 0 ° C to 85 ° C 490 800 ps
Receiver input skew margin
(1)
t
c
= 15.38 ns ( ± 0.2%),
t
RSKM
(see Figure 7 ) |Input clock jitter| <50 ps
(2)
T
A
= –40 ° C to 0 ° C 350 ps
Delay time, input clock to output clock
t
d
t
c
= 15.38 ns ( ± 0.2%) 3.7 ns
(see Figure 7 )
t
c
= 15.38 + 0.75 sin (2 π 500E3t) ± 0.05 ns,
± 80
See Figure 7
Change in output clock period from
∆ t
C(O)
ps
cycle to cycle
(3)
t
c
= 15.38 + 0.75 sin (2 π 3E6t) ± 0.05 ns,
± 300
See Figure 7
t
en
Enable time, SHTDN to phase lock See Figure 8 1 ms
t
dis
Disable time, SHTDN to Off state See Figure 9 400 ns
t
t
Output transition time (10% to 90% t
r
or t
f
) C
L
= 8 pF 3 ns
t
w
Output clock pulse duration 0.43 t
c
ns
(1) t
RSKM
is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this parameter
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) ∆ t
C(O)
is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
5
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