Datasheet

Dn
t
su
CLKIN
t
h
0 V
YP
YM
V
ID
49.9 Ω ±1%
(2 Places)
V
OC
CL = 10 pF MAX
(2 Places)
V
OD(L)
V
OD(H)
V
OC(PP)
0 V
V
OC(SS)
V
OC(SS)
t
f
t
r
100%
80%
20%
0%
NOTE: The lumped instrumentation capacitance for any single ended voltage
measurement is less than or equal to 10 pF. When making measurements at
YP or YM, the complementary output shall be similarly loaded.
SN65LVDS95
www.ti.com SLLS297J –MAY 1998– REVISED MAY 2011
PARAMETER MEASUREMENT INFORMATION
NOTE: All input timing is defined at 1.4 V on an input signal with a 10% to 90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Definition
Figure 3. Test Load and Voltage Definitions for LVDS Outputs
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