Datasheet

SN65LVDS95
SLLS297J –MAY 1998– REVISED MAY 2011 www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
0
Delay time, CLKOUT serial bit position 0 –0.20 0 0.20 ns
t
1
Delay time, CLKOUT↑ serial bit position 1 1/7t
c
–0.20 1/7t
c
+0.20 ns
t
2
Delay time, CLKOUT↑ serial bit position 2 2/7t
c
–0.20 2/7t
c
+0.20 ns
t
c
= 15.38 ns (±0.2%),
t
3
Delay time, CLKOUT↑ serial bit position 3 3/7t
c
–0.20 3/7t
c
+0.20 ns
|Input clock jitter| < 50 ps
(2)
,
t
4
Delay time, CLKOUT↑ serial bit position 4 4/7t
c
–0.20 4/7t
c
+0.20 ns
See Figure 5
t
5
Delay time, CLKOUT↑ serial bit position 5 5/7t
c
–0.20 5/7t
c
+0.20 ns
t
6
Delay time, CLKOUT↑ serial bit position 6 6/7t
c
–0.20 6/7t
c
+0.20 ns
t
sk(o)
Output skew, t
n
–n/7 t
c
–0.20 0.20 ns
t
c
= 15.38 ns (±0.2%),
t
7
Delay time, CLKIN↑ to CLKOUT↑ |Input clock jitter| < 50 ps
(2)
, 4.2 ns
See Figure 5
t
c
= 15.38 ns + 0.75 sin(2π500E3t) ±0.05 ns,
±80 ps
See Figure 6
Δt
C(O)
Output clock cycle-to-cycle jitter
(3)
t
c
= 15.38 ns + 0.75 sin(2π2E6t) ±0.05 ns,
±300 ps
See Figure 6
t
w
High-level output clock pulse duration 4/7 t
c
ns
t
t
Differential output voltage transition time (t
r
or t
f
) See Figure 3 260 700 1500 ps
t
en
Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 7 1 ms
t
dis
Disable time, SHTDN↓ to off-state (CLKOUT low) See Figure 8 250 ns
(1) All typical values are V
CC
= 3.3 V, T
A
= 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
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