Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers LVTTL TSSOP 48

GND

D10

GND

D11

D12

D13

D14

GND

D15

D16

D17

D18

D19

GND

LVDSGND

Y0M

Y0P

Y1M

Y1P

LVDSV

LVDSGND

Y2M

Y2P

CLKOUTM

CLKOUTP

LVDSGND

PLLGND

PLLV

PLLGND

SHTDN

CLKIN

D20

DGG PACKAGE

(TOP VIEW)

SN65LVDS95

www.ti.com

SLLS297J –MAY 1998– REVISED MAY 2011

LVDS SERDES TRANSMITTER

Check for Samples: SN65LVDS95

FEATURES

• 3:21 Data Channel Compression at up to

1.428 Gigabits/s Throughput

• Suited for Point-to-Point Subsystem

Communication With Very Low EMI

• 21 Data Channels Plus Clock in Low-Voltage

TTL and 3 Data Channels Plus Clock Out

Low-Voltage Differential

• Operates From a Single 3.3-V Supply and

250 mW (Typ)

• 5-V Tolerant Data Inputs

• 'LVDS95 Has Rising Clock Edge Triggered

Inputs

• Bus Pins Tolerate 6-kV HBM ESD

• Packaged in Thin Shrink Small-Outline

Package With 20 Mil Terminal Pitch

• Consumes <1 mW When Disabled

• Wide Phase-Lock Input Frequency Range

20 MHz to 68 MHz

• No External Components Required for PLL

• Inputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

• Industrial Temperature Qualified

= –40°C to 85°C

• Replacement for the National DS90CR215

DESCRIPTION

The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out

shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single

integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over

4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.

When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising

edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to

serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT)

are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS95 requires no external components and little or no control. The data bus appears the same at

the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The only

user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut

off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to

a low level.

The SN65LVDS95 is characterized for operation over ambient air temperatures of –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com LVDS SERDES TRANSMITTER Check for Samples: SN65LVDS95 FEATURES 1 • • • • • • • • • • • • • • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential Operates From a Single 3.
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SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com Dn CLKIN ’LVDS95 CLKOUT Previous Cycle Current Cycle Y0 Next D6 D5 D4 D3 D2 D1 D0 D6+1 D13 D12 D11 D10 D9 D8 D7 D13+1 D20 D19 D18 D17 D16 D15 D14 D20+1 D0-1 Y1 D7-1 Y2 D14-1 Figure 1.
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SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT (2) –0.5 V to 4 V VCC Supply voltage range VO Voltage range at any output terminal VI Voltage range at any input terminal Electrostatic discharge (3) –0.5 V to VCC + 0.5 V –0.5 V to 5.
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SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.
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SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT –0.20 0 0.20 ns t0 Delay time, CLKOUT serial bit position 0 t1 Delay time, CLKOUT↑ serial bit position 1 1/7tc–0.20 1/7tc+0.20 ns t2 Delay time, CLKOUT↑ serial bit position 2 2/7tc–0.20 2/7tc+0.20 ns t3 Delay time, CLKOUT↑ serial bit position 3 3/7tc–0.20 3/7tc+0.
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SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION tsu th Dn CLKIN NOTE: All input timing is defined at 1.4 V on an input signal with a 10% to 90% rise or fall time of less than 5 ns. Figure 2. Setup and Hold Time Definition 49.9 Ω ±1% (2 Places) YP VID YM CL = 10 pF MAX (2 Places) VOC NOTE: The lumped instrumentation capacitance for any single ended voltage measurement is less than or equal to 10 pF.
PAGE 8
SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VIH = 2 V and VIL = 0.8 V T CLKIN EVEN Dn ODD Dn (1) The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs. Figure 4. Worst-Case Power Test Pattern t7 CLKIN CLKOUT t6 t5 t4 t3 t2 t1 t0 Yn t7 VOD(H) CLKIN 1.4 V 0V CLKOUT or Xn VOD(L) t0–t6 Figure 5.
PAGE 9
SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Reference + Σ Device Under Test VCO + Modulation v(t) = A sin(2πfmodt) HP8656B Signal Generator, 0.1 MHz–990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz–4200 MHz Modulation Input Device Under Test Output CLKIN CLKOUT DTS2070C Digital Time Scope Input Figure 6. Clock Jitter Test Setup CLKIN Dn ten SHTDN Invalid Yn Valid Figure 7.
PAGE 10
SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS WORST-CASE SUPPLY CURRENT vs FREQUENCY 100 I CC − Supply Current − mA VCC = 3.6 V 80 60 VCC = 3 V VCC = 3.3 V 40 20 0 30 40 50 60 f − Frequency − MHz 70 Figure 9.
PAGE 11
SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 www.ti.com APPLICATION INFORMATION 16-BIT BUS EXTENSION In a 16-bit bus application (Figure 10), TTL data and clock coming from bus transceivers that interface the backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input.
PAGE 12
SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 16-Bit BTL Bus Interface www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS95DGGR Package Package Pins Type Drawing TSSOP DGG 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.8 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS95DGGR TSSOP DGG 48 2000 367.0 367.0 45.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.