Datasheet
www.ti.com
(1) t
RSKM
is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. It is defined by
t
c
14
–tsh.
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN65LVDS94
SLLS298F – MAY 1998 – REVISED JANUARY 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential input voltage threshold 100
mV
Negative-going differential input voltage
V
IT-
-100
threshold
(2)
V
OH
High-level output voltage I
OH
= -4 mA 2.4 V
V
OL
Low-level output voltage I
OL
= 4 mA 0.4 V
Disabled, all inputs open 280 µA
Enabled, AnP at 1 V and AnM at 1.4
V, 62 84 mA
I
CC
Quiescent current (average) t
c
= 15.38 ns
Enabled, C
L
= 8 pF (5 places),
Worst-case pattern, see Figure 4 , 107 mA
t
c
= 15.38 ns
I
IH
High-level input current ( SHTDN) V
IH
= V
CC
±20 µA
I
IL
Low-level input current ( SHTDN) V
IL
= 0 V ±20 µA
I
IN
Input current (A and CLKIN inputs) 0 V ≤ V
I
≤ 2.4 V ±20 µA
I
OZ
High-impedance output current V
O
= 0 V or V
CC
±10 µA
(1) All typical values are V
CC
= 3.3 V, T
A
= 25°C.
(2) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going input voltage threshold only.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Data setup time, D0 through D27 to
t
su
4 6
CLKOUT
C
L
= 8 pF See Figure 5 ns
Data hold time, CLKOUT to D0 through
t
h
4 6
D27
T
A
= 0°C to 85°C 490 800
Receiver input skew margin
(1)
, see t
c
= 15.38 ns (±0.2%),
t
RSKM
ps
Figure 6 |Input clock jitter| <50 ps
(2)
T
A
= -40°C to 0°C 390
Delay time, input clock to output clock, see
t
d
t
c
= 15.38 ns (±0.2%) 3.7 ns
Figure 6
t
c
= 15.38 + 0.75 sin (2 π 500E3t)±0.05 ns,
±80
See Figure 7
Change in output clock period from cycle to
∆ t
C(O)
ps
cycle
(3)
t
c
= 15.38 + 0.75 sin (2 ≠ 3E6t) ±0.05 ns,
±300
See Figure 7
t
en
Enable time, SHTDN to phase lock See Figure 8 1 ms
t
dis
Disable time, SHTDN to Off state See Figure 9 400 ns
t
t
Output transition time (t
r
or t
f
) C
L
= 8 pF 3 ns
t
w
Output clock pulse duration 0.43 t
c
ns
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) ∆ t
C(O)
is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
5
Submit Documentation Feedback