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DESCRIPTION (CONTINUED)
Serial In
CLK
Serial-In/Parallel-Out
Shift Register
A,B, ...G
A0P
A0M
Serial In
CLK
Serial-In/Parallel-Out
Shift Register
A,B, ...G
A1P
A1M
Serial In
CLK
Serial-In/Parallel-Out
Shift Register
A,B, ...G
A2P
A2M
Serial In
CLK
Serial-In/Parallel-Out
Shift Register
A,B, ...G
A3P
A3M
Clock In
CLK
7× Clock/PLL
Clock Out
CLKINP
CLKINM
Control Logic
SHTDN
D0
D1
D2
D3
D4
D6
D7
D8
D9
D12
D13
D14
D15
D18
D19
D20
D21
D22
D24
D25
D26
D27
D5
D10
D11
D16
D17
D23
CLKOUT
SN65LVDS94
SLLS298F – MAY 1998 – REVISED JANUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear
( SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low
level on this signal clears all internal registers to a low level.
The SN65LVDS94 is characterized for operation over ambient air temperatures of -40°C to 85°C.
FUNCTIONAL BLOCK DIAGRAM
2
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