Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - deserialisers LVTTL TSSOP 56

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FEATURES

D22

D23

D24

GND

D25

D26

D27

LVDSGND

A0M

A0P

A1M

A1P

LVDSV

LVDSGND

A2M

A2P

CLKINM

CLKINP

A3M

A3P

LVDSGND

PLLGND

PLLV

PLLGND

SHTDN

CLKOUT

GND

D21

D20

D19

GND

D18

D17

D16

D15

D14

D13

GND

D12

D11

D10

GND

DGG PACKAGE

(TOP VIEW)

DESCRIPTION

SN65LVDS94

SLLS298F – MAY 1998 – REVISED JANUARY 2006

LVDS SERDES RECEIVER

• 4:28 Data Channel Expansion at up to 1.904

Gigabits per Second Throughput

• Suited for Point-to-Point Subsystem

Communication With Very Low EMI

• 4 Data Channels and Clock Low-Voltage

Differential Channels in and 28 Data and

Clock Out Low-Voltage TTL Channels Out

• Operates From a Single 3.3-V Supply and

250 mW (Typ)

• 5-V Tolerant SHTDN Input

• Rising Clock Edge Triggered Outputs

• Bus Pins Tolerate 4-kV HBM ESD

• Packaged in Thin Shrink Small-Outline

Package With 20 Mil Terminal Pitch

• Consumes <1 mW When Disabled

• Wide Phase-Lock Input Frequency Range

20 MHz to 68 MHz

• No External Components Required for PLL

• Meets or Exceeds the Requirements of ANSI

EIA/TIA-644 Standard

• Industrial Temperature Qualified

= -40°C to 85°C

• Replacement for the DS90CR286

The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift

registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single

integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the

SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended

LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the

LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A

phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the

expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 LVDS SERDES RECEIVER FEATURES • • • • • • • • • • • • • • 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out Operates From a Single 3.
PAGE 2
SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control.
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SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 CLKIN Previous Cycle Current Cycle A0 Next Cycle D7 D6 D4 D3 D2 D1 D0 D7+1 D18 D15 D14 D13 D12 D9 D8 D18+1 D26 D25 D24 D22 D21 D20 D19 D26+1 D23 D17 D16 D11 D10 D5 D27 D23+1 D0-1 A1 D86-1 A2 D19-1 A3 D27-1 CLKOUT Dn Dn-1 Dn Dn+1 Figure 1.
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SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) (1) UNIT VCC (2) Supply voltage range -0.3 V to 4 V Voltage range at any terminal (except SHTDN) -0.5 V to VCC + 0.5 V Voltage range at SHTDN terminal -0.
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SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VIT+ Positive-going differential input voltage threshold VIT- Negative-going differential input voltage threshold (2) VOH High-level output voltage IOH = -4 mA VOL Low-level output voltage IOL = 4 mA 0.
PAGE 6
SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION AP VID (VIAP + VIAM)/2 AM VIAP VIC VIAM Figure 2. Voltage Definitions COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE AND VCC 2.5 VIC – Common-Mode Input Voltage – V MAX at >3.15 V MAX at 3 V 2 1.5 1 0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID|– Differential Input Voltage and VCC – V Figure 3.
PAGE 7
SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) T CLKIN/ CLKOUT EVEN Dn ODD Dn Figure 4. Worst-Case Power Test Pattern tsu VOH 70% D0–27 30% VOL th VOH 70% CLKOUT 30% VOL Figure 5.
PAGE 8
SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Tektronix HFS9003/HFS9DG1 Stimulus System (Repeating Patterns 1110111 and 0001000) An D0−D27 DUT CLKIN Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector CLKOUT CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The magnitude of the advance or delay is tRSKM.
PAGE 9
SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Reference + Σ Device Under Test VCO + Modulation v(t) = A sin(2πfmodt) HP8656B Signal Generator, 0.1 MHz–990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz–4200 MHz Modulation Input Device Under Test Output CLKIN CLKOUT DTS2070C Digital Time Scope Input Figure 7. Output Clock Jitter Test Setup CLKIN An ten SHTDN Dn Invalid Valid Figure 8.
PAGE 10
SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 TYPICAL CHARACTERISTICS WORST-CASE SUPPLY CURRENT vs FREQUENCY 140 I CC − Supply Current − mA 120 100 VCC = 3.6 V 80 VCC = 3 V VCC = 3.3 V 60 40 20 0 30 40 50 60 f − Frequency − MHz Figure 10.
PAGE 11
SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 APPLICATION INFORMATION 16-BIT BUS EXTENSION In a 16-bit bus application (Figure 11), TTL data and clock coming from bus transceivers that interface the backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input.
PAGE 12
SN65LVDS94 www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS94DGGR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS94DGGR TSSOP DGG 56 2000 367.0 367.0 45.
PAGE 16
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.