Datasheet
SWITCHING CHARACTERISTICS
1
7
t
c
) 0.20
1
7
t
c
* 0.20
2
7
t
c
) 0.20
2
7
t
c
* 0.20
3
7
t
c
) 0.20
3
7
t
c
* 0.20
4
7
t
c
) 0.20
4
7
t
c
* 0.20
5
7
t
c
) 0.20
5
7
t
c
* 0.20
6
7
t
c
) 0.20
6
7
t
c
* 0.20
Output skew, t
n
*
n
7
t
c
4
7
t
c
PARAMETER MEASUREMENT INFORMATION
Dn
t
su
CLKIN
t
h
CLKSEL LOW
CLKSEL HIGH
SN65LVDS93
SLLS302G – MAY 1998 – REVISED MAY 2009 .................................................................................................................................................................
www.ti.com
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
0
Delay time, CLKOUT ↑ to serial bit position 0 – 0.20 0 0.20 ns
t
1
Delay time, CLKOUT ↑ to serial bit position 1 ns
t
2
Delay time, CLKOUT ↑ serial bit position 2 ns
t
3
Delay time, CLKOUT ↑ serial bit position 3 ns
t
c
= 15.38 ns ( ± 0.2%),
|Input clock jitter| < 50 ps
(2)
,
t
4
Delay time, CLKOUT ↑ to serial bit position 4 ns
See Figure 5
t
5
Delay time, CLKOUT ↑ to serial bit position 5 ns
t
6
Delay time, CLKOUT ↑ to serial bit position 6 ns
t
sk(o)
– 0.20 0.20 ns
t
c
= 15.38 ns ( ± 0.2%),
t
7
Delay time, CLKIN ↓ or CLKIN ↑ to CLKOUT ↑ |Input clock jitter| < 50 ps
(2)
, 4.2 ns
See Figure 5
t
c(o)
Output clock period t
c
ps
t
c
= 15.38 ns + 0.75sin (2 π 500E3t) ±
± 80 ps
0.05 ns, See Figure 6
Δ t
c(o)
Output clock cycle-to-cycle jitter
(3)
t
c
= 15.38 ns + 0.75sin (2 π 3E6t) ±
± 300 ns
0.05 ns, See Figure 6
t
w
High-level output clock pulse duration ps
t
t
Differential output voltage transition time (t
r
or t
f
) See Figure 3 260 700 1500 ps
t
en
Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 7 1 ms
Disable time, SHTDN↓ to off-state (CLKOUT
t
dis
See Figure 8 250 ns
low)
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.
(2) Input clock jitter is the magnitude of the charge in the input clock period
(3) The output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
note: All input timing is defined at 1.4 V on an input signal with a 10% to 90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Definition
6 Submit Documentation Feedback Copyright © 1998 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :SN65LVDS93