Datasheet

ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
SN65LVDS93
www.ti.com ................................................................................................................................................................. SLLS302G – MAY 1998 – REVISED MAY 2009
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
T
Input voltage threshold 1.4 V
|V
OD
| Differential steady-state output voltage magnitude 247 454 mV
R
L
= 100 Ω , See Figure 3
Change in the steady-state differential output voltage
Δ |V
OD
| 50 mV
magnitude between opposite binary states
V
OC(SS)
Steady-state common-mode output voltage See Figure 3 1.125 1.375 V
V
OC(PP)
Peak-to-peak common-mode output voltage 150 mV
I
IH
High-level input current V
IH
= V
CC
20 µ A
I
IL
Low-level input current V
IL
= 0 V ± 10 µ A
V
OY
= 0 V ± 24 mA
I
OS
Short-circuit output current
V
OD
= 0 V ± 12 mA
I
OZ
High-impedance state output current V
O
= 0 V to V
CC
± 20 µ A
Disabled, All inputs at GND 350 µ A
Enabled, R
L
= 100 Ω (5 places),
I
CC(AVG)
Quiescent current (average)
Worst-case pattern (see Figure 4 ), 95 120 mA
t
c
= 15.38 ns
C
i
Input capacitance 3 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.
MIN NOM MAX UNIT
t
c
Input clock period 14.7 t
c
50 ns
t
w
High-level input clock pulse width duration 0.4t
c
0.6t
c
ns
t
t
Input signal transition time 5 ns
t
su
Data setup time, D0 through D27 before CLKIN ↑ or CLKIN ↓ (see Figure 2 ) 3 ns
t
h
Data hold time, D0 through D27 after CLKIN ↓ or CLKIN ↑ (see Figure 2 ) 1.5 ns
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