Datasheet

DESCRIPTION (CONTINUED)
FUNCTIONAL BLOCK DIAGARAM
A,B,...G
SHIFT/LOAD
CLK
Parallel-Load7-Bit
ShiftRegister
7
A,B,...G
SHIFT/LOAD
CLK
Parallel-Load7-Bit
ShiftRegister
7
A,B,...G
SHIFT/LOAD
CLK
Parallel-Load7-Bit
ShiftRegister
7
A,B,...G
SHIFT/LOAD
CLK
Parallel-Load7-Bit
ShiftRegister
7
ControlLogic
7× CLK
CLK
CLKINH
7× Clock/PLL
SHTDN
CLKIN
D27,D5,D10,D11,
D16,D17,D23
D19,D20,D21,D22,
D24,D25,D26
D8,D9,D12,D13,
D14,D15,D18
D0,D1,D2,D3,
D4,D6,D7
Y0P
Y0M
Y1P
Y1M
Y2P
Y2M
Y3P
Y3M
CLKOUTP
CLKOUTM
InputBus
CLKSEL
RISING/FALLING EDGE
SN65LVDS93
SLLS302G – MAY 1998 – REVISED MAY 2009 ................................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
The SN65LVDS93 requires no external components and little or no control. The data bus appears the same at
the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The
only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a
low-level input and the possible use of the shutdown/clear ( SHTDN). SHTDN is an active-low input to inhibit the
clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all
internal registers at a low level.
The SN65LVDS93 is characterized for operation over ambient air temperatures of – 40 ° C to 85 ° C.
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