Datasheet
1
FEATURES
DESCRIPTION
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14
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19
20
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22
23
24
25
26
27
28
56
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46
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40
39
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31
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29
V
CC
D5
D6
D7
GND
D8
D9
D10
V
CC
D11
D12
D13
GND
D14
D15
D16
CLKSEL
D17
D18
D19
GND
D20
D21
D22
D23
V
CC
D24
D25
D4
D3
D2
GND
D1
D0
D27
LVDSGND
Y1M
Y1P
Y2M
Y2P
LVDSV
CC
LVDSGND
Y3M
Y3P
CLKOUTM
CLKOUTP
Y4M
Y4P
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKIN
D26
GND
DGG PACKAGE
(TOP VIEW)
SN65LVDS93
www.ti.com
................................................................................................................................................................. SLLS302G – MAY 1998 – REVISED MAY 2009
LVDS SERDES TRANSMITTER
When transmitting, data bits D0 through D27 are
each loaded into registers upon the edge of the input
• 28:4 Data Channel Compression at up to
clock signal (CLKIN). The rising or falling edge of the
1.904 Gigabits per Second Throughput
clock can be selected via the clock select (CLKSEL)
• Suited for Point-to-Point Subsystem
pin. The frequency of CLKIN is multiplied seven times
Communication With Very Low EMI
and then used to serially unload the data registers in
7-bit slices. The four serial streams and a
• 28 Data Channels Plus Clock in Low-Voltage
phase-locked clock (CLKOUT) are then output to
TTL and 4 Data Channels Plus Clock Out
LVDS output drivers. The frequency of CLKOUT is
Low-Voltage Differential
the same as the input clock, CLKIN.
• Selectable Rising or Falling Clock Edge
Triggered Inputs
• Bus Pins Tolerate 6-kV HBM ESD
• Operates From a Single 3.3-V Supply and
250 mW (Typ)
• 5-V Tolerant Data Inputs
• Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
• Consumes < 1 mW When Disabled
• Wide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
• No External Components Required for PLL
• Outputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
• Industrial Temperature Qualified T
A
= – 40 ° C
to 85 ° C
• Replacement for the DS90CR285
The SN65LVDS93 LVDS serdes (serializer/
deserializer) transmitter contains four 7-bit parallel-
load serial-out shift registers, a 7 נ clock synthesizer,
and five low-voltage differential signaling (LVDS)
drivers in a single integrated circuit. These functions
allow 28 bits of single-ended LVTTL data to be
synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such
as the SN65LVDS94.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998 – 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.