Datasheet

SN65LVDS93A

SLLS992A –AUGUST 2009–REVISED AUGUST 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

PART NUMBER PART MARKING PACKAGE

SN65LVDS93AZQLR LVDS93A in BGA package 56-pin ZQL LARGE T&R

SN65LVDS93ADGG LVDS93A in TSSOP package 56-pin DGG TUBE

SN65LVDS93ADGGR LVDS93A in TSSOP package 56-pin DGG LARGE T&R

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or

refer to our web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

VALUE UNIT

Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC

(2)

-0.5 to 4 V

Voltage range at any output terminal -0.5 to VCC + 0.5 V

Voltage range at any input terminal -0.5 to IOVCC + 0.5 V

Continuous power dissipation See the dissipation rating table

Human Body Model (HBM)

(3)

all pins 5 kV

ESD rating Charged Device Model (CDM)

(4)

all pins 500 V

Machine Model (MM)

(5)

all pins 150 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) All voltages are with respect to the GND terminals.

(3) In accordance with JEDEC Standard 22, Test Method A114-A.

(4) In accordance with JEDEC Standard 22, Test Method C101.

(5) In accordance with JEDEC Standard 22, Test Method A115-A.