Datasheet

SN65LVDS93A

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SLLS992A –AUGUST 2009– REVISED AUGUST 2011

APPLICATION INFORMATION

Power Up Sequence

The SN65LVDS93A does not require a specific power up sequence.

It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to

GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while

all other device blocks are still powered down.

It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device

will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true

input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output

stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still

lower than normal mode.