Datasheet

T
CLKIN
EVENDn
ODDDn
t
7
t
0
t
1
t
2
t
3
t
4
t
5
t
6
CLKIN
CLKOUT
Yn
V
OD(L)
0.00V
t
0-6
t
7
1.40V
~2.5V
~0.5V
CLKIN
CLKOUT
or Yn
V
OD(H)
SN65LVDS93A
SLLS992A –AUGUST 2009–REVISED AUGUST 2011 www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 6. Worst-Case Power Test Pattern
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 7. SN65LVDS93A Timing Definitions
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