Datasheet
Switching Characteristics
1
7
t
c
* 0.2
1
7
t
c
) 0.2
2
7
t
c
* 0.2
2
7
t
c
) 0.2
3
7
t
c
* 0.2
3
7
t
c
) 0.2
4
7
t
c
* 0.2
4
7
t
c
) 0.2
5
7
t
c
* 0.2
5
7
t
c
) 0.2
6
7
t
c
* 0.2
6
7
t
c
) 0.2
Output skew, t
n
*
n
7
t
c
4
7
t
c
SN65LVDS84AQ-Q1
www.ti.com
........................................................................................................................................................ SLLS766A – AUGUST 2006 – REVISED APRIL 2008
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Delay time, CLKOUT ↑ to
t
d0
– 0.2 0.2
serial bit position 0
Delay time, CLKOUT ↑ to
t
d1
serial bit position 1
Delay time, CLKOUT ↑ to
t
d2
serial bit position 2
t
c
= 15.38 ns ( ± 0.2%),
Delay time, CLKOUT ↑ to
ns
t
d3
|Input clock jitter| < 50 ps
(2)
, See Figure 6
serial bit position 3
Delay time, CLKOUT ↑ to
t
d4
serial bit position 4
Delay time, CLKOUT ↑ to
t
d5
serial bit position 5
Delay time, CLKOUT ↑ to
t
d6
serial bit position 6
t
sk(o)
– 0.2 0.2 ns
t
c
= 15.38 ns ( ± 0.2%),
|Input clock jitter| < 50 ps
(2)
, 2.7
See Figure 6
Delay time, CLKIN ↓ to
t
d7
ns
CLKOUT ↑
t
c
= 13.33 ns ~ 32.25 ns ( ± 0.2%),
|Input clock jitter| < 50 ps
(2)
, 1 4.5
See Figure 6
t
c
= 15.38 + 0.308 sin(2 π 500E3t) ± 0.05 ns,
± 62
See Figure 7
Cycle time, output clock
Δ t
c(o)
ps
jitter
(3)
t
c
= 15.38 + 0.308 sin(2 π 3E6t) ± 0.05 ns,
± 121
See Figure 7
Pulse duration, high-level
t
w
ns
output clock
Transition time,
t
t
differential output voltage See Figure 3 700 1500 ps
(t
r
or t
f
)
Enable time, SHTDN↑ to
t
en
See Figure 8 1 ms
phase lock (Yn valid)
Disable time, SHTDN↓ to
t
dis
See Figure 9 6.5 ns
off state (CLKOUT low)
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
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