Datasheet

5 Ω
V
DD
V
DD
R
ESDESD
A B
VCC VCC
SN65LVDS4
SLLSE15 –JULY 2011 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
Values
PARAMETER Units
MIN MAX
Supply voltage range, V
CC
(2)
–0.5 4 V
Receiver output voltage logic level and driver input voltage logic level supply, –0.5 4 V
V
DD
Input voltage range, V
I
(A or B) –0.5 V
CC
+ 0.3 V
Output voltage, V
O
(R) –0.5 V
DD
+ 0.3 V
Differential input voltage magnitude,
1 V
|V
ID
|
Receiver output current, I
O
–12 12 mA
Human-body model electrostatic discharge, HBM ESD
(3)
All pins 2000 V
Bus pins (A, B, Y, Z) 2000 V
Field-induced-charge device model electrostatic discharge, FCDM ESD
(4)
500 V
Continuous total power dissipation, P
D
See the Thermal Information Table
Storage Temperature Range (non operating) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Test method based upon JEDEC Standard 22, Test Method A114-A. Bus pins stressed with respect to GND and V
CC
separately.
(4) Test method based upon EIA-JEDEC JESD22-C101C.
2 Copyright © 2011, Texas Instruments Incorporated