Datasheet

SN65

LVDS4

100 W

SN65LVDS4

www.ti.com

SLLSE15 –JULY 2011

FAILSAFE

One of the most common problems with differential signaling applications is how the system responds when no

differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that

its output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and

within its recommended input common-mode voltage range.

Open circuit means that there is little or no input current to the receiver from the data line itself. This could be

when the driver is in a high-impedance state or the cable is disconnected. When this occurs, it is recommended

to have an external failsafe solution as shown in Figure 21. In the external failsafe solution, the A side is pulled to

via a weak pullup resistor and the B side is pulled down via a weak pulldown resistor. This creates a voltage

offset and prevents the receiver from switching based on noise.

Figure 21. Open-Circuit Failsafe of the LVDS Receiver

R1 and R3 Calculation With VCC = 1.8 V

Assume that an external failsafe bias of 25 mV is desired

Bias current in this case is = 25 mV/100 Ω = 250 µA

Next, determine the total resistance from VCC to ground = 1.8 V/250 µA = 7.2 kΩ

Keeping the common mode bias of 1.25 V to the receiver, the value of R3 = 1.25 V/250 µA = 5 kΩ

Thus, R1 = 2.2 kΩ

R1 and R3 Calculation With VCC = 2.5 V

Assume that an external failsafe bias of 25 mV is desired

Bias current in this case is = 25 mV/100 Ω = 250 µA

Next, determine the total resistance from VCC to ground = 2.5 V/250 µA = 10 kΩ

Keeping the common mode bias of 1.25 V to the receiver, the value of R3 = 1.25 V/250 µA = 5 kΩ

Thus, R1 = 5 kΩ